في إتش دي إل

-- (this is a VHDL comment)

-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;

-- this is the entity
entity ANDGATE is
   port (
         IN1 : in std_logic;
         IN2 : in std_logic;
         OUT1: out std_logic);
end ANDGATE;
architecture RTL of ANDGATE is

begin

  OUT1 <= IN1 and IN2;

end RTL;

entity mux1b4X1 is
    port(in1,in2,in3,in4,c1,c2:in Bit;out1:out Bit);
end mux1b4X1;

architecture struk_mux1b4X1 of mux1b4X1 is
    signal c1_n,c2_n,intk11,intk12,intk13,intk14:Bit;
    
    component o_not 
       port(in1:in Bit ;out1:out Bit);
    end component ;
    
    component o_3and is
       port(in1,in2,in3:in Bit; out1:out Bit);
    end component ;
    
    component o_4or is
       port(in1,in2,in3,in4:in Bit; out1:out Bit);
    end component ;    
    
begin
    KNc1:o_not
    port map(in1=>c1,out1=>c1_n);
    
    KNc2:o_not
    port map(in1=>c2,out1=>c2_n);
    
    Kand11:o_3and
    port map(in1=>in1,in2=>c1_n,in3=>c2_n,out1=>intk11);
    
    Kand12:o_3and
    port map(in1=>in2,in2=>c1,in3=>c2_n,out1=>intk12);
    
    Kand13:o_3and
    port map(in1=>in3,in2=>c1_n,in3=>c2,out1=>intk13);
    
    Kand14:o_3and
    port map(in1=>in4,in2=>c1,in3=>c2,out1=>intk14);
    
    Kor:o_4or
    port map(in1=>intk11,in2=>intk12,in3=>intk13,in4=>intk14,out1=>out1);
    
end struk_mux1b4X1;

entity mux1b4X1 is
    port(in1,in2,in3,in4,c1,c2:in Bit;out1:out Bit);
end mux1b4X1;

architecture sprav_mux1b4X1 of mux1b4X1 is
begin
    process(in1,in2,in3,in4,c1,c2)
    begin
       if c1='0' and c2='0' then
         out1<=in1;
       elsif c1='1' and c2='0' then
         out1<=in2;
       elsif c1='0' and c2='1' then
         out1<=in3;
       elsif c1='1' and c2='1' then
         out1<=in4;
       end if;
    end process;
end sprav_mux1b4X1;

-- latch template 1:
Q <= D when Enable = '1' else Q;

-- latch template 2:
process(D,Enable)
begin
  if Enable = '1' then
    Q <= D;
  end if;
end process;

-- SR-latch template 1:
Q <= '1' when S = '1' else
  '0' when R = '1' else Q;

-- SR-latch template 2:
process(S,R)
begin
  if S = '1' then
    Q <= '1';
  elsif R = '1' then
    Q <= '0';
  end if;
end process;

-- This one is a RS-latch (i.e. reset dominates)
process(S,R)
begin
  if R = '1' then
    Q <= '0';
  elsif S = '1' then
    Q <= '1';
  end if;
end process;

-- simplest DFF template (not recommended)
Q <= D when rising_edge(CLK);

-- recommended DFF template:
process(CLK)
begin
  -- use falling_edge(CLK) to sample at the falling edge instead
  if rising_edge(CLK) then
    Q <= D;
  end if;
end process;
  
-- alternative DFF template:
process
begin
  wait until rising_edge(CLK);
  Q <= D;  
end process;

-- template for asynchronous reset with clock enable:
process(CLK, RESET)
begin
  if RESET = '1' then   -- or '0' if RESET is active low...
    Q <= '0';
  elsif rising_edge(CLK) then
    if Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

-- template for synchronous reset with clock enable:
process(CLK)
begin
  if rising_edge(CLK) then
    if RESET = '1' then 
      Q <= '0';
    elsif Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

-- simple D-type flip-flop
process(CLK)
begin
  if rising_edge(CLK) then  
    Q <= D;  
  end if;
end process;

-- BAD VHDL: this does NOT make the flip-flop a DFF without a reset!!
process(CLK, RESET)
begin
  if RESET = '1' then  
  	-- do nothing. Q is not set here...  
  elsif rising_edge(CLK) then  
    Q <= D;  
  end if;
end process;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type

entity counter_example is
generic (WIDTH : integer = 32);
port (
  CLK, RESET, LOAD : in std_logic;
  DATA : in unsigned(WIDTH-1 downto 0);  
  Q : out unsigned(WIDTH-1 downto 0));
end entity counter_example;

architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  Q <= cnt;

  process(RESET, CLK)
  begin
    if RESET = '1' then
      cnt <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD = '1' then
        cnt <= DATA;
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;
end architecture counter_example_a;

-- Fib.vhd
--
-- Fibonacci number sequence generator

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Fibonacci is
port (
    Reset       : in    std_logic;
    Clock       : in    std_logic;
    Number      : out   unsigned(31 downto 0)
);
end entity Fibonacci;

architecture Rcingham of Fibonacci is

    signal  Previous    : natural;
    signal  Current     : natural;
    signal  Next_Fib    : natural;

begin

    Adder:
    Next_Fib <= Current + Previous;

    Registers:
    process (Clock, Reset) is
    begin
        if Reset = '1' then
            Previous <= 1;
            Current  <= 1;
        elsif rising_edge(Clock) then
            Previous <= Current;
            Current  <= Next_Fib;
        end if;
    end process Registers;

    Number <= to_unsigned(Previous, 32);

end architecture Rcingham;